The power consumption in an Application Specific Integrated Circuity (ASIC) and other similar integrated circuits comes mainly from two sources, namely, dynamic power and static power (i.e., leakage). The dynamic power consumed by the ASIC is the power consumed by the ASIC due to circuit switching to perform the desired task(s). In other words, dynamic power consumption is the power consumption due to active circuitry within the ASIC during operation. In contrast, the static power consumption of the ASIC is power consumption due to current(s) that constantly flow through the ASIC as long as the ASIC is powered and is not related to the actual task(s) that are performed by the ASIC. In other words, the static power consumption is the power consumption of the circuitry within the ASIC when inactive.
The trend is that leakage becomes a larger part of the power consumption of the ASIC as the technology used to fabricate the ASIC goes down, or reduces, in geometry. As a result, it is becoming more and more important to manage leakage for power consumption sensitive ASICs such as, for example, ASICs found in mobile devices (e.g., mobile phones).
Currently, there are several techniques that are used to reduce leakage. The most common of these techniques is power gating of power domains. More specifically, power domains are time controlled by software. The software de-activates, or powers down, a power domain when the software knows that no hardware block within the power domain needs power based on a defined use case(s). The software activates, or powers on, a power domain when, based on the currently running use case, the software knows that a hardware block(s) within the power domain needs power. The activation time for a power domain includes the time required by the software to make the decision to activate the power domain, the time needed for state changes handled via interrupt, and the time needed to control the power switches for the power domain. Further, a large safety margin must be added such that the power domain is activated before the hardware block(s) are accessed. In other words, the power domain must be powered a relatively long period of time before the hardware block(s) in the power domain are to be accessed. As a result, the power domains are activated, or powered, longer than needed.
For example, FIG. 1 illustrates a Hardware (HW) system 10 including five HW blocks 12-1 through 12-5 (generally referred to collectively as HW blocks 12 and individually as HW block 12) as well as a ring bus 14 including a separate Ring Bus Interface (RBI) 16-1 through 16-5 (generally referred to collectively as RBIs 16 and individually as RBI 16) for each of the HW blocks 12-1 through 12-5. The HW blocks 12-1 through 12-5 are connected to the corresponding RBIs 16-1 through 16-5 via corresponding Input Output Sockets (IOSs) 18-1 through 18-5 (generally referred to collectively as IOSs 18 and individually as IOSs 18). FIG. 1 also illustrates an example of the active times of the HW blocks 12. If each HW block 12 is implemented in a separate power domain that is activated or de-activated via software in the conventional manner, the software needs to have good control of when the HW blocks 12 are active as well as handle the power up and power down time of the corresponding power domains. With the overhead for power up of the power domains and controlling the activation time via interrupt or other mechanism, the most likely solution is that all of the HW blocks 12 are powered on all the time.
Thus, there is a need for an improved system for controlling power consumption, and in particular leakage, in an integrated circuit.
U.S. Pat. No. 7,443,759 entitled “Reduced-Power Memory with Per-Sector Ground Control” discloses selective power control of sectors comprised in a reduced-power memory. The selective power control selects a sector of the memory to power-up in response to a subset of address bits for accessing the memory and individually powers up the selected sector by decreasing ground potential for the selected sector from a retention level to an access level.
U.S. Patent Application Publication No. 2008/0025123 entitled “Interface Circuit System and Method for Autonomously Performing Power Management Operations in Conjunction with a Plurality of Memory Circuits” discloses an interface circuit that is in communication with memory circuits and a system. The interface circuit autonomously performs a power management operation in association with at least a portion of the memory circuits. In particular, a memory circuit in a non-accessed state is identified. A power saving operation, such as power down, is initiated for the identified memory circuit.
International Patent Application Publication No. WO 2008/017625 entitled “Distributed Autonomous Power Management in a Memory System” discloses a control unit that autonomously manages power within and for a group of memory devices.
These references relate to reduction of power consumption in a memory system and do not relate to powering up and powering down of hardware power domains.